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- 用vhdl编写的带fifo的uart，西电自动化系的作业-The vhdl write uart with fifo
MCTP1
- Vhdl 同步FIFO设计 该FIFO 实现方案比传统方式简单,工作速度频率高-Vhdl synchronous FIFO design of the FIFO implementations simpler than traditional, high working speed frequency
Ram_FIFO
- VHDL硬件语言实现FIFO，管道,经过测试，很好用-VHDL hardware language FIFO, pipe
syn_fifo
- 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
syn_fifo_use
- fpga 同步fifo调用 vhdl语言编写syn fifo use -synchronous fifo call fpga vhdl language syn fifo use
xfft_v3_2_pipe_64
- vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
t4_fifo
- FIFO的verilog与VHDL的实现，并与FIFO的IP核做对比，为了方便大家学习，每个文件均附有测试脚本文件，希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test scr ipt file, we want to be useful.
UART_FIFO
- 用VHDL语言实现内置FIFO的UART，并做时序仿真和功能仿真确定正确与否。-Implement a built in FIFO UART using VHDL language, and do functional simulation and timing simulation to determine correct.
proje2
- it is code for implement the FIFO in VHDL. FIFO is first in first out memory.
asyn_FIFO-
- A asynchronous FIFO is implemented. VHDL fil+ vsim.do scr ipt
TransfData
- 用于FPGA发送数据，采用VHDL语言编程，采用16位fifo发送，内涵时钟、复位、使能信号-FPGA is used to send data, using VHDL language programming, using 16 fifo sent connotation clock, reset, enable signal
code
- 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, di
fifo_srl_uni
- asynchronous fifo in vhdl
FIFO_TXD
- fifo标准协议接受代码，基于fpga，vhdl语言-fifo standard protocol accepted code, based on fpga, vhdl language
uartlvds
- UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
VHDL_RAM_FIFO_ROM
- VHDL代码实现FIFO从ROM中读取数据然后传输到RAM中-VHDL code for FIFO read data ROM to RAM and then transfer
fifo_control
- vivado project file for fifo in vhdl